1. Field of the Invention
The present invention relates to active balun circuits, and more particularly, to an active balun circuit that can improve symmetry between two complementary output signals by rejecting common-mode noise.
2. Description of the Related Art
In general, balun circuits convert single input signals (unbalanced signals) into differential output signals (balanced signals) or vice versa. The balun circuit is divided into a passive balun having passive elements and an active balun having active elements according to which elements constitute the balun circuit.
FIG. 1 is a configuration view illustrating an active balun circuit according to the related art.
An active balun circuit, shown in FIG. 1, according to the related art includes a load circuit unit 10, a differential amplifying unit 20, and a current source 30. The load circuit unit 10 includes a first load LD1 and a second load LD2 that are connected in parallel with a power supply Vdd. The differential amplifying unit 20 includes a first MOS transistor Ml and a second MOS transistor M2. The first MOS transistor Ml has a drain connected to the first load LD1 of the load circuit unit 10 and a gate connected to an input terminal IN. The differential amplifying unit 20 has a drain connected to the second load LD2 of the load circuit unit 10, a gate connected to a ground, and a source connected to a source of the first MOS transistor Ml. The current source 30 is connected between a common connection node of the sources of the first and second MOS transistors Ml and M2 of the differential amplifying unit 20, and maintains a constant current flowing through the differential amplifying unit 20.
In the active balun circuit according to the related art, when a signal that is input through the input terminal IN passes through the first and second MOS transistors M1 and M2, a phase of the input signal is inverted. A signal that is in phase with the input signal is output through a first output terminal OUT1 connected to the drain of the first MOS transistor M1. On the other hand, a signal that is out-of-phase with the input signal is output through a second output terminal OUT2 connected to the drain of the second MOS transistor M2.
The two output signals travel along different signal transmission paths from the input terminal IN to the first output terminal OUT1 and the second terminal OUT2. The output signals have different phase and amplitude shifts due to different parasitic capacitance components or different impedances along the different signal transmission paths. As a result, symmetry between the two output signals is deteriorated.